Current theory...
We seem to be clear that the output directories do not already exist on disk. A possible solution, for platforms which know what mkdir -p means, would then be
# compile src files$(OBJSDIR)/%.o: %.c mkdir -p $(@D) # Make the output directory, even if it already exists @echo 'Building file: $<' @echo 'Invoking: Cross ARM C Compiler' arm-none-eabi-gcc $(CFLAGS) $(INCDIRS) -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@""$<" @echo 'Finished building: $<' @echo ''For handling the problem of creating directories under Windows or Linux, I'd suggest using the solution of this question.
First theory...
You need to compare the invocations of gcc with the manual. In particular, since the makefile cannot find the dependency, we are interested in that part that creates said file:
-MF"$(@:%.o=%.d)" -MT"$@"The -MF specifies where the dependency file will be written. However,
An -MT option will set the target to be exactly the string you specifyI don't think you want that. Deleting -MT"$@" may be sufficient to solve your current problem.
If not, would you be willing to create a reproducible test case? I can read the current makefile, but short of setting up rather a lot of supporting files, I can't test any suggested fixes.
edit: Though I like the above theory, it appears to be incorrect. Removing | inserting the -MT string has no obvious effect on my own makefiles.